الکترونیکا پروژه های الکترونیک و مکانیک

برنامه رفتاریش به شکل زیر خواهد بود:
library ieee;
use ieee.std_logic_1164.all;

----------------------------------------------

entity JK_FF is
port ( clock: in std_logic;
J, K: in std_logic;
reset: in std_logic;
Q, Qbar: out std_logic
);
end JK_FF;

-----------------------------------------------

architecture behv of JK_FF is

-- define the useful signals here

signal state: std_logic;
signal input: std_logic_vector(1 downto 0);

begin

-- combine inputs into vector
input <= J & K;

p: process(clock, reset) is
begin

if (reset='1') then
state <= '0';
elsif (rising_edge(clock)) then

-- compare to the truth table
case (input) is
when "11" =>
state <= not state;
when "10" =>
state <= '1';
when "01" =>
state <= '0';
when others =>
null;
end case;
end if;

end process;

-- concurrent statements
Q <= state;
Qbar <= not state;

end behv;

به صورت ساختاری هم این شکلی میشه:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JK_FF_VHDL is
port( J,K: in std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end JK_FF_VHDL;

architecture Behavioral of JK_FF_VHDL is
signal temp: std_logic;
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
elsif (J='1' and K='1') then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral;
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